Digital Logic Design
Spring 2007
Instructor: Dr. M. Bag-Mohammadi
Email: mozafarb@ece.ut.ac.ir
Assistant: Ms. Sadeghian
Web log: click here
Office Hours: Click here
Grade: Digital Design, Laboratory
Text: Digital Design by Mano (3rd Edition). The CD-ROM in the back of the book contains a Verilog simulator as well as source code files for all the examples in the book.
Goals
Primary goals of the course are:
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To introduce digital logic design. |
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Specific topics include: Binary systems, Boolean algebra, logic gates, analysis/design of combinatorial circuits, synchronous sequential logic, (If we had enough time we will look at registers, counters, and memory briefly).. |
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To introduce laboratory experiments in digital circuits and logic design; students will construct and test basic digital circuits using standard integrated circuits (ICs). |
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There will be 1 exam during the semester and a final exam at the end of the semester. |
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All exams will be open book and open notes. |
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Assignments are due seven days from the initial day of the assignment (i.e. the following Tuesday). |
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Late homework will be docked 50% per class period late, unless approved arrangements are made in advance. |
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All coursework must be clear, legible, and have the name, course, and assignment number in the upper right hand corner of the page. |
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Cooperative group study on the homework is encouraged, but simply copying someone else's work is unethical and will leave you unprepared for exams. |
| Topic | Word File | Solution |
| Introduction: Binary Systems, Boolean Algebra and Logic Gates, Gate-Level Minimization | hw1-s07.doc | |
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Combinatorial logic, decoder, multiplexer, Nand implementation |
hw2-s07.doc | |
| Sequential circuit | hw3-s07.doc | |
| Design of Sequential circuit | hw4-s07.doc |
Final grades in the course will be based on the following weighting distribution.
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Homework……20% |
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Midterm 1…… 35% |
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Final Exam…..50% |
Students are responsible for their own learning, through reading and studying the text, reviewing the lectures, and working out the homework problems. I strongly advise that you read the upcoming material before it appears in lecture; the material will make much more sense that way.
| Topic | Chapter | Lecture Note |
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Introduction: Binary Systems |
1 | dlc-1.ppt |
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Boolean Algebra and Logic Gates |
2 | dlc-2.ppt |
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Gate-Level Minimization: Karnaugh
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3 | dlc-3.ppt |
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Gate-Level Minimization |
3 | dlc-4.ppt |
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Gate-Level Minimization, Combinational Logic |
4,3 | dlc-5.ppt |
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Combinational Logic |
4 | dlc-6.ppt |
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Combinational Logic |
4 | dlc-7.ppt |
| Midterm group 1 | 1,2,3,4 | midterm-s07.doc |
| Midterm group 2 | 1,2,3,4 | midterm2-s07.doc |
| Sequential circuit | 5 | dlc-8.ppt |
| Sequential circuit | 5 | dlc-9.ppt |
| Sequential circuit | 5 | dlc-10.ppt |
| register, | 6 | dlc-11.ppt |
| counter | 6 | dlc-12.ppt |
| Lab | - | lab.doc |