Digital Electronic
Spring 2010
Email: mozafarb@ece.ut.ac.ir
Web log: click here
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Digital circuit Design |
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Basic knowledge of electrical circuits |
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lCMOS
devices and manufacturing technology
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lCMOS gates |
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cCombinational and sequential circuits |
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lArithmetic building blocks |
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lInterconnect |
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lMemories |
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Propagation delay, noise margins, power |
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Timing and clocking |
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Design methodologies |
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There will be 1 exam during the semester and a final exam at the end of the semester. |
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All exams will be open book and open notes. |
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Assignments are due seven days from the initial day of the assignment (i.e. the following Sunday). |
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Late homework will be docked 50% per class period late, unless approved arrangements are made in advance. |
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All coursework must be clear, legible, and have the name, course, and assignment number in the upper right hand corner of the page. |
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Cooperative group study on the homework is encouraged, but simply copying someone else's work is unethical and will leave you unprepared for exams. |
| Topic | Word File |
| CMOS Inverter, CMOS logic | Hw1-dic10.doc, Hw1-dic-v2-10.doc |
| Course review | Hw2-dic-10.doc |
Final grades in the course will be based on the following weighting distribution.
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Homework……5% |
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Final Exam…..95% |
Students are responsible for their own learning, through reading and studying the text, reviewing the lectures, and working out the homework problems. I strongly advise that you read the upcoming material before it appears in lecture; the material will make much more sense that way.
| Topic | Chapter | Lecture Note |
| Introduction | 1 | lec1-dic.ppt |
| Design Metrics | 1 | lec2-dic.ppt |
| Manufacturing Process | 2 | lec3-dic.ppt |
| IC process: A graphical view, ( thanks to Mr. Kikhaei ) | 2 | lec3b-dic.pptx |
| Design Rules | 2 | lec4-dic.ppt |
| Inverter Design | 5 | lec5-dic.ppt |
| Combinational logic design-CMOS Logic | 6 | lec6-dic.ppt |
| Other static logics | 6 | lec7-dic.ppt |
| Dynamic logics | 6 | lec8-dic.ppt |
| Sequential logic | 7 | lec9-dic.ppt |
| Final | 1-7 |